Integrated circuits that enter low power or sleep modes conventionally leave power on to internal registers, memory devices, low voltage detection circuits, and the like, in order to preserve the state of the device. Therefore, even in sleep modes, integrated circuit systems can still consume at least 100 nanoamperes (nA) of power due to systems remaining powered along with leakage current. For certain battery powered devices, this level of power consumption is unacceptable.
One conventional way for dealing with this problem is to use non-volatile memory, e.g., electrically erasable programmable read only memory (EEPROM). For example, before a central processing unit (CPU) enters a sleep mode it can store various amounts of state information to a non-volatile memory, like EEPROM. After which, the CPU enters into a low current or no current sleep mode that may not include a supply voltage monitor since the information is stored to non-volatile memory. However, one of the problems associated with this conventional solution is the latency to resume when the device wakes up from the sleep mode.
As such, it is desirable to address one or more of the above issues.